There's at least a topic discussing this at: http://electronics.stackexchange.com/questions/23089/pcb-test-patterns-to-assess-etch-quality
The first picture shows a portion of that PDF
As you can see it is not free of troubles. The QFP64 pins are spaced strangely, the 0.2 and 0.3 traces routed between the QFP32 pins is touching the pads, the 0.2 trace going out the corner as well.
The author claims to be an exercise and I don't argue with that, but some errors seem to be provoked by the layout software (EDA).
First, the printer capabilities need to be checked:
The 0.1mm width traces are a bit wider than needed (about 0.2) and the traces between the QFP32 pins are merged all together. All clearances under 0.1 are impossible to maintain. Everything else seems ok.
Going quickly through the steps described yesterday as I did not take enough pictures.
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| Taping the glossy paper on the printer paper |
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| Resulting print |
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| Taping the board on the glossy paper |
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| Cutting the excess paper before lamination |
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| Folding paper to increase lamination pressure |
The result seems to mirror the printer capabilities. The area on the top right was not properly degreased so the toner came quickly off. The features are even wider now because of the extra laminating pressure and/or temperature, but anything lower than that will cause the toner to rip off.
The "Raster" text does not have any more
Still, 0.1 mm traces are fine, QFP32 would be fine if no traces are running through the pads. Minimum spacing is 0.2mm but a safer value would be at 0.5.
QFP64 and traces between QFP32 pads could be obtained with some modified footprints. The pad width (0.4 and 0.5) can be reduced because it will spread out anyway. This would make component placement critical but should not pose any problems. It would also reduce the risk of shorts between adjacent pads.
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